Inside the Neo Geo AES+ ASIC Controversy

The announcement of the Neo Geo AES+ was supposed to be a celebration: a modern, premium recreation of SNK’s legendary 1990s home console, marketed as a true hardware revival rather than an emulation box. Instead, it has ignited one of the most technical and passionate debates the retro hardware scene has seen in years, centered on claims that the console’s custom chips are derived from an existing MiSTer FPGA core.

This dispute mixes engineering nuance, marketing language, and community expectations. To understand why it matters, you need to know what ASICs and FPGAs are, why MiSTer is so central to modern retro gaming, and why purists care deeply about what is—or isn’t—inside the shell of a recreated console.

Why the Neo Geo AES+ Matters to Retro Fans

For many enthusiasts, Neo Geo hardware represents the pinnacle of 2D arcade gaming. The original AES console and its arcade sibling, the MVS, were technically advanced for their time and powered some of the most iconic fighting and action games ever made. Genuine hardware is increasingly expensive, fragile, and hard to maintain, which is why a high-end recreation like the Neo Geo AES+ immediately attracted attention.

The AES+ project has been promoted as a premium product that:

• Runs original Neo Geo cartridges, not ROMs on flash storage
• Reproduces the original system’s timing and behavior at the hardware level
• Uses newly designed ASICs instead of software emulation or generic FPGA boards
• Aims to deliver “as close as possible” to original console behavior

On paper, that pitch is tailored precisely to the hardcore audience that cares about authenticity and preservation. That is also exactly why the current controversy has hit so hard: the value proposition rests almost entirely on how the internal electronics have been created.

ASIC vs FPGA in Plain Language

At the core of the argument are two types of digital hardware used to replicate classic systems: ASICs and FPGAs. They are often contrasted, but technically they are related tools in the same design chain.

What is an FPGA?

A Field-Programmable Gate Array (FPGA) is a reconfigurable chip that can be programmed to behave like different hardware circuits. Engineers describe how a system works using a hardware description language (HDL), and that design is compiled into a configuration that programs the FPGA’s internal logic resources. Because the configuration can be changed, the same physical chip can implement many different designs across its lifetime.

• Reprogrammable: Can be updated or replaced with new logic after manufacturing.
• Ideal for prototyping: Commonly used to test designs before manufacturing fixed chips.¹
• Used in MiSTer: The popular MiSTer platform uses an FPGA to replicate many retro systems.

What is an ASIC?

An Application-Specific Integrated Circuit (ASIC) is a custom chip designed to perform a specific set of functions. Once manufactured, an ASIC’s logic is fixed; it cannot be reprogrammed like an FPGA. Modern ASIC design often begins with the same HDL descriptions used for FPGAs, but the final step is a costly fabrication process that turns those designs into a permanent silicon implementation.²

• Fixed behavior: The logic is “hard-wired” and cannot be updated in the field.
• High upfront cost: Mask and fabrication costs are substantial, but per-unit cost can be low at scale.
• Better efficiency: Custom chips can outperform and use less power than general-purpose solutions for a specific task.

How They Relate to Retro Hardware

Original 1990s consoles, including the Neo Geo AES, were built from a mix of standard chips and custom ASICs that implemented graphics, sound, and system glue logic. Modern recreations typically choose one of three strategies:

1. Software emulation on a general-purpose CPU (e.g., running an emulator on Linux).
2. FPGA implementation that recreates the hardware logic in a reprogrammable chip.
3. New ASICs derived from a modern hardware design, potentially based on an earlier FPGA implementation.

The Neo Geo AES+ positions itself firmly in the third category: newly manufactured ASICs, described as re-engineered versions of the original hardware rather than an FPGA platform. The debate centers on whether those ASICs are genuinely fresh, independent designs or silicon implementations of an existing community-developed MiSTer core.

The MiSTer Platform and the Neo Geo Core

MiSTer is an open-hardware and open-source platform built around an Intel/Altera FPGA board (DE10-Nano) that aims to replicate classic computers, consoles, and arcade boards at the hardware level.³ For many systems, MiSTer has become the reference standard among accuracy-focused players.

The Neo Geo core on MiSTer is the product of considerable community effort, gradually improved through:

• Study of original schematics where available
• Reverse engineering of physical boards and chips
• Systematic comparison against original hardware for timing and audio/visual behavior

Like other MiSTer cores, it is distributed as HDL source code under open licenses. In practice, that means anyone can inspect, study, or build on the design, subject to license terms. However, there remains a strong cultural expectation in open-source communities that commercial use should be transparent and respectful of contributors.

What the Neo Geo AES+ Promises Technically

Marketing materials for the AES+ have emphasized that it is not:

• A traditional software emulation device
• A generic FPGA board running community cores

Instead, the messaging highlights “legacy” or “re-engineered” ASICs designed to reproduce the behavior of the original Neo Geo’s graphics and system logic chips. In practical terms, this means the device should:

• Accept original AES cartridges and run them with cycle-accurate timing
• Offer compatibility with existing televisions or HDMI displays via modern outputs
• Behave like the original console in terms of memory mapping, audio mixing, sprite handling, and CPU interaction

From a consumer perspective, the promise is relatively simple: plug in your game, and it should behave just as it did on a genuine Neo Geo, without input lag, blurry scaling, or audio desyncs that can happen with poorly implemented emulation.

The Allegation: “Basically the MiSTer Core Broken Up Into Chips”

Controversy erupted when an FPGA developer publicly argued that the AES+ ASICs appear to be based on existing MiSTer core code. According to this viewpoint, the chips inside the new system are not entirely new designs created from scratch, but rather silicon implementations of the same hardware description that already powers MiSTer’s Neo Geo core—just partitioned into several ASICs instead of residing on a single FPGA.

The criticism goes further, suggesting this constitutes a kind of “bait and switch”: marketing suggests a bespoke ASIC-based recreation distinct from FPGA work, while in practice the internal design might be heavily derived from community-led FPGA code. The core points behind this argument include:

• Design reuse: Modern ASICs can indeed be produced directly from HDL designs originally written for FPGAs.²
• Partitioning logic: A monolithic FPGA design can be split across multiple ASICs that replicate different subsystems (graphics, system control, I/O, etc.).
• License and attribution concerns: If community HDL was used, critics expect explicit acknowledgement and clarity about how it was integrated.

From a purely engineering standpoint, using a mature, well-tested MiSTer core as a starting point is technically sensible. It can accelerate development and leverage years of community refinement. The controversy is less about technical feasibility and more about how that process is represented, credited, and communicated to buyers.

Why Marketing Language Became a Flashpoint

The clash between expectations and messaging is amplified by a few key factors:

To many retro hardware fans, the value of the AES+ is closely tied to its perceived engineering authenticity. If the system is viewed as a polished, premium case around a MiSTer-derived design, some may question whether it justifies its price or marketing emphasis. Transparent communication about design lineage—whether or not MiSTer code is involved—would go a long way toward defusing suspicion.

Is Using MiSTer Code a Problem in Itself?

Reusing MiSTer HDL in an ASIC is not inherently problematic. Modern chip design flows often reuse IP cores or open-source blocks as building components.² The key issues are:

• License compliance: Respecting the legal terms of the cores used (which may include attribution, sharing modifications, or restrictions on commercial use, depending on license).
• Clear messaging: Avoiding an impression that a design is entirely original if it builds substantially on community work.
• Community goodwill: Recognizing the debt to volunteers and potentially contributing improvements back to the ecosystem.

From a player’s perspective, a MiSTer-derived ASIC could be a strong positive—MiSTer cores are often praised for their accuracy. The downside is the loss of field-upgradability: an ASIC based on MiSTer logic cannot be patched to fix bugs in the same way an FPGA implementation can. Any remaining inaccuracies become permanent quirks of the hardware.

What This Means for Buyers

For someone considering the Neo Geo AES+, the debate raises several practical questions.

Questions to Ask Before Buying

• How transparent is the vendor about the internal design? Do they clearly explain how the custom ASICs were developed?
• Is there a track record of technical disclosures? Detailed documentation, developer interviews, or whitepapers can signal seriousness.
• What is the update story? If an issue is discovered—such as timing glitches or audio inaccuracies—how will it be addressed on fixed hardware?
• How important is hardware purity to you personally? If MiSTer-level accuracy in a polished shell satisfies you, provenance may matter less.

Advantages a Well-Executed AES+ Could Offer

• Industrial design and build quality that exceeds DIY FPGA setups
• Plug-and-play cartridge support with modern outputs and interfaces
• Potentially lower latency and more predictable behavior than software emulation boxes

Potential Drawbacks to Consider

• Irreversible hardware bugs if ASIC behavior proves inaccurate
• Possibility of limited transparency about design origins
• Premium pricing compared with MiSTer or emulation-based alternatives

Broader Implications for Retro Hardware Preservation

The AES+ debate is part of a larger conversation about how we preserve and re-experience classic systems. Governments and cultural organizations increasingly recognize video games and hardware as heritage artifacts.⁴ As original hardware ages, replacements and recreations inevitably rely on modern design methodologies, from FPGA-based re-implementations to ASICs derived from HDL.

Key trends shaping this space include:

• Growing dependence on community reverse engineering: Hobbyist work often fills gaps left by incomplete or unavailable official documentation.
• Commercialization of community IP: Companies build products on open-source cores, sometimes clashing with community expectations.
• Need for durable solutions: Long-term preservation may favor simpler, well-documented designs that can be reproduced by future engineers.

Handled well, projects like the AES+ can help bridge the gap between fragile original hardware and future-proof recreations. Handled poorly, they can erode trust with precisely the communities that make such efforts viable.

Frequently Asked Questions

Is the Neo Geo AES+ using software emulation?

Based on available information, the AES+ is not positioned as a software emulation device. Instead, it is said to rely on custom ASICs that directly implement hardware logic, more akin to a console built from modernized versions of the original chips than a PC running an emulator.

Could a MiSTer core really be turned into an ASIC?

Yes. MiSTer cores are written in HDL, the same class of languages used to design commercial chips. That code can be fed into an ASIC design flow, with appropriate adaptation and optimization, to produce fixed-function silicon that behaves like the original FPGA implementation.²

Does using community FPGA code automatically make a product illegitimate?

No. Many successful products incorporate open-source IP. The key ethical and legal questions revolve around respecting licenses, giving credit where due, and being honest with customers about what they are buying.

Is a fixed ASIC better than a reprogrammable FPGA for accuracy?

Not inherently. Accuracy depends on the quality of the underlying design. An FPGA can be more flexible because it allows updates if inaccuracies are discovered. An ASIC can be more efficient but locks in whatever behavior it implements, including potential flaws.

Should I wait for more hardware analysis before buying an AES+?

For risk-averse buyers, waiting for independent teardowns and side-by-side testing against original Neo Geo hardware and MiSTer is a sensible approach. Objective measurements of timing, audio, and video behavior will clarify how well the system lives up to its claims.